A high-speed serial data signal can be transmitted through transmission lines from a transmitter to a receiver without an accompanying clock signal. A clock data recovery (CDR) circuit in the receiver generates clock signals from an approximate frequency reference signal, and then phase-aligns the clock signals with respect to the data signal. The receiver uses the clock signals to sample data bits in the data signal.
The Stratix® IV GX field programmable gate array (FPGA) manufactured by Altera Corporation of San Jose, Calif., includes a CDR circuit that functions in lock-to-data mode and lock-to-reference mode. In lock-to-data mode, the CDR circuit adjusts the phases of its output clock signals based on the phase of the input data signal. In lock-to-reference mode, the CDR circuit adjusts the phases and frequencies of its output clock signals based on the phase and the frequency of a reference clock signal using a phase-locked loop (PLL) circuit.
The Stratix® IV GX field programmable gate array (FPGA) circuit uses an external voltage-controlled crystal oscillator (VCXO) circuit to generate a recovered clock signal. The Stratix® IV GX FPGA circuit includes a receiver circuit, a transmitter circuit, a first-in-first-out (FIFO) buffer circuit, a phase and frequency detector (PFD) circuit, and a phase-locked loop (PLL) circuit.
An input data signal (Data In) is provided to an input of the receiver circuit, as serial data bits. The data rate of the Data In signal may be 270 megabits per second (Mbps), for instance. The Data In signal is transmitted according to a standard for video interfaces referred to as Standard-Definition Serial Digital Interface (SD-SDI). The receiver circuit and the transmitter circuit function according to the standard for SD-SDI. The receiver circuit samples data bits in the Data In signal to generate sampled data bits. The receiver circuit de-serializes the sampled data bits to generate parallel data bits in parallel data signals. The receiver circuit asserts a logic high pulse in a data valid signal for each 10-bit data word that is sampled in the Data In signal. The data valid signal is a periodic signal having a frequency of approximately 27 megahertz (MHz), in this instance.
The receiver circuit contains a CDR circuit that generates a recovered clock signal. The Stratix® IV GX does not support input data signals having data rates of less than 600 megabits per second (Mbps). In order to support data rates less than 600 Mbps, the receiver circuit oversamples the Data In signal 11 times, and the CDR circuit remains in lock-to-reference mode. Because the CDR circuit does not operate in lock-to-data mode, the recovered clock signal is not phase adjusted based on the phases of data bits in the Data In signal.
The external VCXO circuit generates a low jitter clock signal having a frequency of 148.5 MHz. The low jitter clock signal is provided to inputs of the receiver circuit, the transmitter circuit, and the PLL circuit. The CDR circuit in receiver circuit generates the recovered clock signal in response to the low jitter clock signal generated by the VCXO circuit.
The PLL circuit generates a clock signal having a frequency of 27 MHz in response to the low jitter clock signal generated by the VCXO circuit. The clock signal generated by the PLL is provided to inputs of the transmitter circuit, the FIFO buffer circuit, and the PFD circuit. The PFD circuit compares the phase and frequency of the clock signal generated by the PLL circuit to the phase and frequency of the data valid signal generated by the receiver circuit to generate a control voltage signal. The PFD circuit generates the control voltage based on the differences between the phase and frequency of the data valid signal and the phase and frequency of the clock signal generated by the PLL circuit. The VCXO circuit varies the phase and frequency of the low jitter clock signal based on changes in the control voltage signal. The PFD circuit causes the VCXO circuit to adjust the phase and frequency of the low jitter clock signal to cause the phase and frequency of the clock signal generated by the PLL circuit to match the phase and frequency of the data valid signal.
The FIFO buffer circuit stores the parallel data signals from the receiver circuit as stored data bits in response to the recovered clock signal and the data valid signal. The FIFO buffer circuit outputs the stored data bits, in parallel to the transmitter, in response to the clock signal generated by the PLL. The transmitter circuit serializes the received data bits to generate serial data bits and transmits the serial data bits in response to the clock signal generated by the PLL and the low jitter clock signal generated by the VCXO circuit.
If the Data In signal has a data rate of exactly 270 Mbps, and the recovered clock signal has a frequency of exactly 148.5 MHz, the data valid signal has an average frequency of 27 MHz, and the data valid signal has a fixed pattern of pulses that is repeated as long as the data rate of the Data In signal remains at exactly 270 Mbps. According to this repeating fixed pattern of pulses, the data valid signal is in a logic high state for 1 cycle of the recovered clock signal, then in a logic low state for 4 cycles of the recovered clock signal, then in a logic high state for 1 cycle of the recovered clock signal, and then in a logic low state for 5 cycles of the recovered clock signal (i.e., 1H, 4L, 1H, 5L, . . . ).
The serial data rate of the Data In signal is not always exactly 270 Mbps. If the Data In signal has a data rate that is not exactly 270 Mbps, and the recovered clock signal has a frequency of exactly 148.5 MHz, the pattern of pulses in the data valid signal varies. For example, if the Data In signal has a data rate of slightly less than 270 Mbps, the data valid signal has the following pattern of pulses, 1H, 4L, 1H, 5L, 1H, 5L, 1H, 4L, 1H, 5L . . . . If the data rate of the Data In signal is slightly greater than 270 Mbps, the data valid signal has the following pattern of pulses, 1H, 4L, 1H, 5L, 1H, 4L, 1H, 4L, 1H, 5L . . . .
Thus, the data valid signal has large phase variations when the data rate of the Data In signal is not exactly 270 Mbps. Therefore, the data valid signal cannot be used by a PLL to generate a system clock signal or a clock signal that is provided to external components. Also, external VCXO circuits are costly and require extra board space.